1. Field of the Invention
Embodiments of the present invention relate to a method of manufacturing a non-volatile memory device. More particularly, embodiments of the present invention relate to a method of manufacturing a non-volatile memory device having a blocking layer exhibiting reduced leakage current.
2. Description of the Related Art
In general, semiconductor memory devices may be classified as either volatile or non-volatile memory devices. Volatile memory devices, e.g., dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices, may have relatively high input/output (I/O) speeds, and may lose data stored therein when power is shut off. In contrast, non-volatile memory devices, e.g., read-only memory (ROM) devices, electrically erasable programmable ROM (EEPROM) devices, and/or flash EEPROM devices, may have relatively slow I/O speeds, and may be able to maintain data stored therein even when power is shut off.
In the conventional non-volatile memory device, data may be electrically stored, i.e., programmed or erased, through a Fowler-Nordheim (F-N) tunneling mechanism and/or through a channel hot electron injection mechanism. Further, the conventional non-volatile memory device may be classified as either a floating gate type or a charge trap type, e.g., silicon-oxide-nitride-oxide semiconductor (SONOS) devices or metal-oxide-nitride-oxide semiconductor (MONOS) devices. The floating gate type non-volatile memory device may include a gate structure and source/drain regions on a semiconductor substrate.
More specifically, the conventional gate structure of the floating gate type non-volatile memory device may include a tunnel insulation layer, a floating gate electrode, a blocking layer, and a control gate electrode, while the blocking layer may have a multilayered dielectric structure including a silicon nitride layer between two silicon oxide layers.
Attempts have been made to form a blocking layer using a metal oxide layer instead of the silicon nitride layer. However, use of a metal oxide layer between two silicon oxide layers may increase diffusion of materials between the metal oxide layer and the silicon oxide layers, thereby deteriorating interface morphology therebetween. A deteriorated morphology between the layers of the blocking layer may increase leakage current through the blocking layer, thereby reducing operability and reliability of the non-volatile memory device.